1. Field of the Invention
The invention relates to integrated circuits. More particularly, the invention relates to an apparatus for delay calibration of a forward clock for use in data capture at a receiving end.
2. Description of the Related Art
As operating speeds of processors and computer systems increase, communication between components such as memories and I/O devices must increase to reduce or eliminate bottleneck problems. One solution to this communications problem is to provide a source-synchronous environment in which components of a system operate. A source-synchronous timing architecture, also called clock forwarding, sends a forward clock or strobe signal along with data. The forward clock is then used to capture the data at receiving end. In a source-synchronous environment, data transfers may occur on both edges of the forward clock and therefore may have a higher transfer rate than other systems.
To capture the data in a register using the forward clock, the forward clock needs to be delayed to satisfy the data setup time requirement of the register. For 100 MHz memory devices, the required delay time is approximately ¼ period of the forward clock, i.e. 2.5 nsec. In general, delay elements are used to provide proper delay for clocking the data into a register. A prior art scheme programs an adjustable delay element at the factory so that the adjustable delay element may delay a forward clock by a fixed interval in aftertime. However, delay elements tend to have drift due to heat, aging, and other environmental factors. It is unfortunate that the prior art cannot compensate for these variations after shipping so the data setup time requirement may be unsatisfied. This causes the forward clock to clock the data into the register incorrectly.
Therefore, what is needed is a novel technique for automatic calibration delay of the forward clock.